While the I²C interface seems simple on the surface, this straightforward architecture is not immune to intermittent glitches, device misbehaviors, and protocol violations. Tracking down these errors can be tedious business if the right tool is not utilized.
The CAS-1000-I2C/E bus analyzer is a bloodhound when it comes to sniffing out I²C irregularities. The ability to spot complex problems and identify invisible obstacles make it the preferred I²C development solution. Advanced logging, debugging, emulation, and verification capabilities offer power and versatility, yet the Windows-based user interface makes the most complex features simple to use.
The CAS-1000-I2C/E succeeds where simple monitoring and interactive I/O tools fall short—a complete solution to monitoring, emulating, stressing, and characterizing I²C and SMBus interfaces.
- Supports I2C and SMBus monitoring and traffic generation for Standard-mode, Fast-mode, Fast-Mode Plus (Fm+) with I2C bus data rates up to 5 Mbit/s
- Supports High-Speed mode (Hs-mode) monitoring
- Simultaneous monitoring and emulation—up to 1 emulated master and 10 emulated slaves, all running concurrently
- Measures common I2C bus electrical and timing parameters, complete with a graphical waveform display
- Injects glitch and signal patterns, protocol errors, and slave clock stretching to override the bus and stress the UUT
- Programmable bus voltage reference and software configurable pull-up resistors on the SDA and SCL lines
- Powerful command and script language for emulation control and automated testing
- Passive traffic monitoring with state and timing recording
- Unlimited and continuous logging of transaction data to file
- Time stamping, message filtering, and symbolic translating
- Programmable trigger event to highlight and display bus transactions of interest
- In-System Programming of I2C serial EEPROMs
- High-speed, bus-powered USB 2.0 interface
- I2C Exerciser software supports Microsoft Windows 7, Windows 8/8.1 and Windows 10 operating systems
The CAS-1000-I2C/E is an advanced, feature-packed and powerful I2C debugging and analysis system. By providing full visibility as well as detailed control of the I2C bus, the CAS-1000-I2C/E enables engineers to save time and resources, replacing multiple instruments with a single intuitive and specialized tool. The Corelis hardware and software provide a convenient easy to use environment for hardware debugging, software development, bus validation, and in-system programming.
Passively listens and records all I2C bus traffic while displaying captured data in real time in both state and waveform timing windows. Virtually unlimited trace data recording capability. Includes message filtering, symbolic translation, and event triggering. Bus signal and protocol conformance are continually evaluated with deviations flagged. The monitor window is shown below.
The CAS-1000-I2C/E leaves standard serial bus analyzers behind by providing a complete, peerless set of tools to generate bus traffic, inject glitches and protocol errors, measure bus electrical and timing parameters, program serial EEPROMs, emulate I2C masters and slaves, and more—all while simultaneously monitoring the bus, logging trace and timing data, and verifying I2C bus behavior on the fly. The I2C Exerciser software interface, included with the CAS-1000-I2C/E, provides a consolidated and intuitive GUI (Graphical User Interface) for host PC control and visualization of all bus monitoring and traffic generation features.
I2C Parameters Scope
Using the Parameters Scope tool, the CAS-1000-I2C/E can be utilized to quickly measure and return the basic electrical and I2C timing parameters of the target bus without setting up the advanced scripting functions of the Test tool. It can gather master specific and slave-specific parameters, such as signal timing characteristics, and also system-wide parameters, such as bus voltage, pull-up resistance, and capacitance. Each measurement is compared to maximum and minimum values loaded from a specification file and the resulting pass or fail status is shown with the measurement. The Parameters Scope provides the additional ability to display a graph of captured signal edge transition data and a trigger can be set to capture a particular I2C bus signal’s rising or falling edge.
Enables concurrent virtual devices programmed to interact with the bus in addition to those of the target. These can include a Master (capable of multi-master arbitration), and up to 10 slaves. The above monitor includes and tags this emulated traffic.
Interprets a script program file to control a go-no-go test sequence, including bus electrical/timing parametric measurements. This enables automatic target bus specification compliance and functionality validation. It is suitable for design/development as well as factory acceptance testing. The test script window is shown below.
A user interactive bus I/O access portal. This enables individual bus transfers for immediate target communications. Looping supports repeated I/O patterns to facilitate external signal observations. Besides generic writing and reading of data blocks, a growing library of known standard devices is included showing interactive screens tailored to the device’s organization (such as ADCs, DACs, flash memories, SMbus behavior, etc.). The debugger window is shown below.
Provides easy-to-use high-speed in-system programming of I2C compatible serial EEPROMs. Two programmer windows are shown below.
One application of the CAS-1000-I2C/E is to rapidly validate compliance of a target bus with the specification. This is supported at the electrical, timing, as well as the signaling level. Another application is to passively monitor any I/O activity transpiring on a target bus. This includes the detection of errant protocol. All such logged information is time stamped for history reconstruction. A third application is the programmed interchange of messages with the target bus system, also recorded by the monitoring function. This method can serve to generally exercise the target bus. It also supports target code development with debug stand-ins for non-existent bus devices. Finally, a general user PC to I2C communications link provides quick and direct visibility/control of target devices. This is extended to user applications via the provided API.
The System Management Bus, or SMBus, was defined by Intel® Corporation in 1995 and is based on the I2C bus architecture. It is used in personal computers and servers for low-speed system management communications.
SMBus is a two-wire interface through which simple system and power management related chips can communicate with the rest of the system. A system using SMBus as a control bus for these system and power management related tasks passes messages to and from devices by addressed transfers, enabling moderate transfer rates using minimal board resources. With System Management Bus, for example, a device can provide manufacturer information, tell the system what its model/part number is, save its state for a suspend event, report different types of errors, accept control parameters, and return its status. The SMBus may share the same host device and physical bus with standard I2C components. Intel originally conceived the SMBus as the communication bus to accommodate Smart Batteries and other system and power management components.
The CAS-1000-I2C/E software features SMBus decoding for common SMBus devices. Ordinarily, the raw data of the I2C transactions between SMBus devices must be manually decoded into meaningful information. With the SMBus decoding feature, a specific device address can be associated with a text file containing decoding information which allows the I2C Exerciser software to do the interpretation automatically.
The CAS-1000-I2C/E also supports SMBus PEC (Packet Error Checking) message generation.
At the core of the CAS-1000-I2C/E is an on-board engine whose logic performs the low level interaction with the I2C bus. This element receives set-up, direction and drive data from the host via a USB 2.0 port. Conversely, as bus activity is detected and characterized, its transitional information is conveyed up to the host for further processing.
The PC host operates this processor via the USB 2.0 port under the provided Windows application. Alternatively, the user may create custom software which calls included API C/C++ library routines to easily operate the I2C I/O, avoiding hardware management details.
In addition there is an array of onboard physical interface elements to facilitate the required measurement, capture, and operating capabilities. This includes a number of DACs to develop the various programmable voltages.
High-speed A2D converters enable the capture of I2C bus waveforms for analysis, including sensing adjustable thresholds (with hysteresis), signal level crossing detection, and transition time determination.
Programmable Clock Rate
The CAS-1000-I2C/E clock rate is programmable under software for use when emulating a master. It is capable of supporting standard mode and fast mode transfers of up to 5 Mbits/sec as well as intermediate values. For emulated slaves, clocking comes from the target, whose rate is automatically accommodated up to 5 MHz since the clock rate automatically tracks the target bus master.
Test Discrete I/O Signals
Two programmable lines can be operated under PC host software control. They are available to stimulate the target system or sense target conditions in coordination with the testing. Each line is programmable as input, output, or output open-drain. One of these outputs can be a dedicated trigger and programmably linked to the SMB output trigger connector for test synchronization with external laboratory equipment. The other discrete I/O can be tied to the other SMB connector as an input trigger.
Adjustable Voltage Levels
The signal level of the set of discrete I/O and trigger lines is programmable from 1.25V to 3.3V in increments of 50mV. The I2C bus reference voltage can be programmed as target driven through its bus pull-ups or driven from the CAS-1000-I2C/E I2C analyzer. This target reference voltage can also be measured. When the CAS-1000-I2C/E is programmed to source this reference level (both SCL and SDA signals), the voltage can be set with 100mV resolution over the range of 0.8V to 5V. When the CAS-1000-I2C/E reference voltage drives the bus, one of a set of pull-up resistors can be selected. The resistor values span the range from 250 to 50K ohms. Additionally, sensed bus signal high and low individual threshold levels can be adjusted. This supports the bus hysteresis requirements. Default software-determined values are available.
Auxiliary TAP Port
The CAS-1000-I2C/E includes an IEEE-1149.1 JTAG Test Access Port (TAP). This port can be used to perform boundary-scan testing and in-system programming of flash, EEPROMs and PLDs on the target system and is both hardware and software compatible with the complete ScanExpress™ family of IEEE-1149.1 test and in-system programming products offered by Corelis. This feature is mutually exclusive to the I2C functionality and requires it to be put into the JTAG mode.
* Note: The I2C bus is also often referred to as IIC bus, Philips I2C bus, Inter-IC bus, 2-wire bus, 2-wire serial bus, two-wire bus, or SMBus.
|Mechanical Dimensions||5.48 x 1.00 x 4.66 (+/- 0.25) inches|
|Shipping Weight||7 pounds (approximate)|
|Certifications||RoHS Compliant , CE Marked|
|USB Transfer Rate||High-speed USB 2.0|
|USB Cable||Ships with a 6 foot USB 2.0 A to B cable|
|I2C Bus Connector||RJ45 (AMP P/N 406549-1)|
|I2C Bus Cable||Ships with a 12 inch interface cable that termi-nates in flying leads suitable for connection to 0.025” square posts. Test clips are included.|